1. Field of the Invention
The invention relates generally to a circuit configuration and method of manufacturing programmable memory devices. More particularly, this invention relates to an improved circuit configuration and method for manufacturing a five-volt one-time programmable (OTP) memory cells.
2. Description of the Relevant Art
As more and more one-time programmable memory devices are employed for post packaging trimming operations, a person of ordinary skill in the art is still facing the challenge that a high voltage, i.e., a voltage greater than five volts, is required to program the OTP devices. This poses a potential device safety issue for low voltage devices operating at a voltage lower than the trimming voltage as higher trimming voltage may cause damage on those devices rated at a lower voltage. Furthermore, the production cost for the OTP is increased due to the requirement that extra masks are necessary to produce high voltage CMOS circuit. The high voltage circuit required for the OTP devices also causes the trim circuit to occupy greater die area on the silicon that also causes the increase in production costs.
There are increasing demands for precision power management products and circuits with reduction in power supply voltage and higher frequency of operation. Devices such as band-gap circuits and switched mode power supplies require output voltage or frequency with precise control and the precision requirements are becoming more stringent in modern power circuits. In the past, the precise control was obtained by using wafer level trim techniques such as metal/poly fuses and forward/reverse trimming of Zener diodes. However, under many circumstances, the wafer trim techniques are not sufficient to satisfy the precision requirements even after the chip is packaged due to the additional stress and charges induced by the packaging processes. Due to this reason, there is a need for post package trimming using one-time programmable devices.
Most prior art post package trim techniques use an NMOSFET with a floating gate that is coupled to the control gate through a coupling capacitor implemented with a double poly stacked gate structure where the partial overlap of floating gate and control gate forms the coupling capacitor. The operational principle is to collect electrons in the floating gate and shift the threshold voltage of the NMOSFET. The electrons are collected using different techniques such as Fowler-Nordheim tunneling and HCI hot carrier injection. To improve the tunneling efficiency and lower the trimming voltage, different techniques are applied to enhance the electrical field in the carrier injection region. Such techniques include the implementation of a stacked gate structure where a portion of floating gate oxide is thinned to improve electron-collecting capability. However the removal of partial gate oxide requires extra etching step therefore increases the cost.
The One-time programmable (OTP) devices for post package trimming usually are processed at the same time as the functional circuit using standard CMOS technologies. For improving the hot-carrier degradation in the mainstream sub-micron CMOS technologies, a sidewall spacer with lightly doped drain (LDD) implant is used to reduce the drain to substrate field at the drain end of the channel. However, in order to increase the efficiency of electron injection into the floating gate of an NMOS, a higher drain field becomes necessary. A coupling PMOS transistor is then employed as a coupling a capacitor.
FIG. 1A is a cross sectional view for showing the NMOS transistor on the left that coupled to a PMOS transistor on the right functioning as a coupling capacitor. Referring to FIG. 1B for an equivalent circuit of the OTP device of FIG. 1A that can be implemented optionally with a double poly EPROM. FIG. 1C shows an I-V diagram for illustrating the program operation that shows the different I-V characteristics before and after an OTP program process. The programming voltage on the gate is typically 10 to 13 volts. For this reason, a high voltage (HV) circuit that can sustain such higher voltage ranges is required. Additionally, the OTP device further requires a high voltage electrostatic discharge (ESD), i.e., HV-ESD, protection circuit. In order to make the HV circuit, the NMOS requires additional N+ implant on the drain region to increase hot carriers. The OTP device further require a low programming current with a read voltage at approximately 1.5 volts, i.e., Vg=5V/Vd=1.5 V. A typical programming time is less than 100 μsec.
Referring to FIG. 2A for a functional block diagram of a trimming system implemented with a conventional trim diode that employs a reverse bias diode to lower the trimming current as that shown in FIG. 2B with an equivalent circuit of OTP array shown in FIG. 2C. The programming voltage on the Vcc is typically 6-12 volts and therefore requires a high voltage configuration. As shown in FIGS. 2B and 2C, a high voltage NMOS, i.e., HV NMOS driver, is required to operate the trimming circuit thus requiring a large area for the trimming driver to sustain higher programming current in the range of 5 to 100 mA with typical programming time of one to ten μsec. Since the reverse bias diode is significantly smaller for easy trimming when comparing with the size of the NMOS due to the fact that the NMOS needs large channel width to support large trimming current, C1 is much smaller than C2 and an ESD spike would mostly applied to C1. In order to prevent false trimming operations caused by ESD events, a snap-back circuit across the trim diode is required which may in turn compete with the trim diode resulting the difficulty in making the device.
Another one-time programmable (OTP) memory is disclosed in another co-pending patent application Ser. No. 11/122,848 assigned to a common Assignee of this Application on May 5, 2005, the disclosures made in that Application is hereby incorporated by reference in this Application. A one-time programmable (OTP) memory cell is disclosed by taking advantage of the sidewall and corner breakdown features of a thin oxide layer overlying a polysilicon segment. The phenomena of etch undercut that occurs prior to a processing step of gate oxidation further degrades the breakdown property of the thin oxide. It is a common practice in the processes of manufacturing a integrate circuit (IC) device to take special care for preventing the development of the vulnerable points caused by the inter-poly breakdown due to the etch undercut phenomenon. Specifically, special attention is required in fabricating the conventional IC poly-poly capacitors or flash/EEPROM memory to prevent the breakdown vulnerability in these inter-poly coupling layers. Such special requirements may include an implementation of the high quality oxide-nitride-oxide composite layers as that commonly practiced in the electronic device manufacturing processes. Conversely, as disclosed in this invention, the weakness of the inter-poly sidewall oxide breakdown that commonly considered as an undesirable feature is utilized to realize an advantageous structural feature to more conveniently carry out an enhanced programming mechanism for the OTP cell. With a thin oxide layer covering an undercut corner to conveniently induce a breakdown, the conductivity between two polysilicon layers can be more conveniently generated. The poly segment sidewall configuration that commonly considered as undesirable structural feature is implemented for inducing a breakdown and for changing the conductivity state to perform the one-time program function. A high programmable voltage in the range of 15-20 volts is required. Therefore, a high voltage driver circuit preferably made of HV PMOS driver is required and the driver is also coupled with the HV selection NMOS circuits. The OTP can be operated with low programming current of approximately one mA with programming time of about one μsec. Manufacture of such OTP memory requires additional poly mask and the transfer of the manufacturing processes to other technologies depends on the inter-poly oxide layer thickness between two polysilicon layers and the breakdown voltage requirement.
Another one-time programmable (OTP) memory is disclosed in another co-pending patent application Ser. No. 11/518,001 filed by common Inventors of this Application on Sep. 7, 2006, the disclosures made in that Application is hereby incorporated by reference in this Application. A single poly one-time programmable (OTP) memory cell is disclosed that includes a first and second MOS transistor sharing the gate, drain and source region by applying a drift region implantation to delineate the first and second MOS transistors. The drift region implanted with a P-dopant is diffused into the channel regions from under the source and drain to counter dope a lightly dope drain region. The dopant profile of the drift region implanted is gradually decreased and ended at the boundary between the first and second MOS transistors thus creating a higher threshold voltage for the first MOS transistor with a higher level of dopant concentration and maintaining the same threshold voltage for the second MOS transistor functioning as a regular NMOS through the farther end of the first MOS transistor that has a decreased level of dopant concentration and LDD region. The OTP memory is connected to a coupling capacitor via the single polysilicon stripe. The coupling capacitor is implemented in a preferred embodiment as a PMOS complementary to the NMOS transistors of the OTP memory device in a common N-well. The P-drift region implanted for the OTP transistor is also simultaneously implanted as a source and drain for the coupling capacitor formed as a PMOS device. The programming voltage on the gate of the OTP is approximately 10-13 volts thus requiring HV trimming circuit and HV ESD protection circuits. The OTP memory can be operated with low programming currents and is programmed approximately less than 100 μsec. The manufacture processes require a high voltage P-drift mask and a transfer of such device into other technologies depends on the process in forming the HV P-drift regions in the technologies.
Therefore, a need still exists in the fields of circuit design and device manufactures for providing a new and improved circuit configuration and manufacturing method to provide the OTP memory with trimming circuits that can operate at approximately five volts. Specifically, a need still exists to provide new and improved OTP that can be trimmed at approximately five volts such that the standard 5-volts CMOS manufacturing processing technology can be applied without adding extra masks thus achieving cost savings and resolve the above discussed technical difficulties and limitations.